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Snr Principal Analog Engineer
年収：応相談
採用企業案件
SiTime Japan合同会社
-
- 会社規模非公開
- その他
| 部署・役職名 | Snr Principal Analog Engineer |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
The Principal Analog Mixed-Signal Design Engineer contributes to building precision timing circuits, leveraging SiTime’s industry-leading MEMS technology. These products have applications ranging from high-performance Networking and Communications Infrastructure to ultra-low power Mobile platforms, including wearable devices. It is not necessary to meet all job requirements to be a qualified candidate for the position. Responsibilities: • Contribute to the architectural definition of the design and chip integration • Technical leader for chip level design and verification simulations to ensure building blocks meet specifications at the schematic level and after post-layout extraction, while fully provisioning for DFT and DFM • Work closely with Layout Engineers to validate proper layout, using all best-known methods • Document assigned blocks, and hold preliminary and final design review meetings • Actively participate in the chip bring-up, evaluation and characterization, with emphasis on owned blocks • Work cross-functionally with Product, Characterization, Test, and Application Engineers on issues related to owned circuit blocks • Coach, mentor and develop junior/mid-level analog designers, foster cross-functional collaboration. |
| 労働条件 |
Probation Period: Yes (3 months) Working Hours: 9:00 AM – 6:00 PM (1-hour break). Flexible working hour provided Work Location: Shinagawa Headquarters Holidays: Saturdays, Sundays, and public holidays Leave: Annual paid leave (10 days granted after 6 months of employment) Expected annual income: 9,000,000 yen – Commuting Allowance: Provided according to company policy Social Insurance: Health insurance, welfare pension, workers’ compensation insurance, employment insurance, 401K |
| 応募資格 |
【必須（MUST）】 • M.S. in Electrical Engineering or related field with minimum 15 years of related experience, or Ph.D. in Electrical Engineering with minimum 12 years of related experience• Excellent academic record with published research projects prototyped and proven in silicon • Detailed knowledge of CMOS circuits and noise analysis • Core expertise in one of the following areas: • Integer-N and fractional-N PLL • Sigma-Delta ADCs • Temperature sensor • Analog and digital filters • Quartz or MEMS oscillator • Sub-threshold circuits • Low noise regulator and bandgap • High-speed output drivers • Ability to oversee circuit layout for critical blocks • Knowledge of programming languages: MATLAB, VerilogA • Proficient in using Cadence analog design tools • Good facilitation skill for project/design review meeting • Excellent analytical, problem-solving, written/verbal communication. • Proven leadership and ability to collaborate across system architects, digital teams, layout, test, manufacturing 【歓迎（WANT）】 • Passionate, self-starter with a strong commitment to flawless execution• Excellent written and verbal communication skills required • Ability to work well with others in a fast-paced collaborative team environment |
| アピールポイント | 成果報酬型 マネジメント業務なし 完全土日休み フレックスタイム |
| 受動喫煙対策 | 喫煙室設置 |
| 更新日 | 2025/12/23 |
| 求人番号 | 6410212 |
採用企業情報
- SiTime Japan合同会社
-
- 会社規模非公開
- その他
-
会社概要
【本社所在地】東京都港区港南１丁目８−２７ 日新ビル ３階
【事業内容】微小電子機械システム（MEMS）及びアナログ半導体の研究及び開発
転職・求人情報の詳細をご覧になる場合は会員登録（無料）が必要です