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Senior Verification Engineer
年収：900万 ～ 2000万
採用企業案件
SiTime Japan合同会社
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- 会社規模非公開
- その他
| 部署・役職名 | Senior Verification Engineer |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
About SiTime SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. Job Summary As a Senor Verification Engineer, you will be part of a team developing MEMS timing ICs. It is not necessary to meet all job requirements to be a qualified candidate for the position. Responsibilities: • Developing SV-RNM models for both analog and mixed-signal circuits • Developing verification plan from chip or block specifications • Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.) • Developing digital-top verification in System Verilog • Defining and writing System Verilog Assertions (SVA) • Defining and writing functional coverages and covergroups • Running simulations and debugging simulation results • Reviewing verification results for Tape-out sign-off • Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas |
| 労働条件 |
Probation Period: Yes (3 months) Working Hours: 9:00 AM – 6:00 PM (1-hour break). Flexible working hour provided Work Location: Shinagawa Headquarters Holidays: Saturdays, Sundays, and public holidays Leave: Annual paid leave (10 days granted after 6 months of employment) Expected annual income: 9,000,000 yen – 20,000,000 yen Commuting Allowance: Provided according to company policy Social Insurance: Health insurance, welfare pension, workers’ compensation insurance, employment insurance, 401K |
| 応募資格 |
【必須（MUST）】 • MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry• Good verbal and written communication skills in English • Proficient in SystemVerilog and SystemVerilog OOP • Fluency in utilizing scripting languages such as Perl / Python • Proficient (through work experience) in verification using UVM • Strong experience writing SystemVerilog Assertions (SVA) • Understanding of Analog schematic and experience with Cadence Virtuoso • Basic understanding of digital design using Verilog • Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers • Ability to work independently and drive solutions to challenging problems 【歓迎（WANT）】 • Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques• Experience with UVM-AMS methodology • Solid experience with Formal Property Verification (FPV) • Programming experience writing OOP code in C++ • Excellent written and verbal communication skills in English • Experience with performing analog mixed-signal verification • Proven track record in working well with others in fast-paced and collaborative work environment • Knowledge of analog design • Knowledge of synthesizable digital design • Experience working on verification of datapath designs including filters • Passionate, self-starter with a strong commitment to flawless execution • Excellent written and verbal communication skills required • Ability to work well with others in a fast-paced collaborative team environment |
| アピールポイント | 海外事業 成果報酬型 マネジメント業務なし 完全土日休み フレックスタイム |
| 受動喫煙対策 | 喫煙室設置 |
| 更新日 | 2025/12/24 |
| 対象年齢 | 35歳 ～ 44歳 |
| 年齢制限理由 | 技能等の継承のため労働者数の少ない年齢層を対象とするため / 省令３号のロ |
| 求人番号 | 6410135 |
採用企業情報
- SiTime Japan合同会社
-
- 会社規模非公開
- その他
-
会社概要
【本社所在地】東京都港区港南１丁目８−２７ 日新ビル ３階
【事業内容】微小電子機械システム（MEMS）及びアナログ半導体の研究及び開発
転職・求人情報の詳細をご覧になる場合は会員登録（無料）が必要です