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Senior Analog Engineer
年収：800万 ～ 2000万
採用企業案件
SiTime Japan合同会社
-
- 会社規模非公開
- その他
| 部署・役職名 | Senior Analog Engineer |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
• Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications • Perform transistor-level design and simulation using industry leading EDA tools • Lead comprehensive design reviews • Supervise Analog Circuit Physical Design Layout and edit layouts • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release • Perform post-layout parasitic-extraction and back-annotated simulations to validate design • Perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality and yields • Participate in the bring-up of silicon prototypes • Initiate Design-of Experiments for Root Cause Analysis, anomalous observations in silicon across PVT conditions, and propose solutions |
| 応募資格 |
【必須（MUST）】 • B.Sc. with 8 years of experience, or M.Sc. with 3 years of experience or Ph.D. with 1 years of experience in Electrical Engineering• Proven track record at each stage of the following: • Circuit architecture development and technical feasibility studies • Writing detailed block-level specifications and review documents • Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps,regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture • Support product teams to take the design to production • Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL • Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers • Extensive experience with post-layout extraction and verifications • Experience with validation, characterization, qualification, and adherence to production release criteria • Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers • Ability to work independently and drive solutions to challenging problems |
| アピールポイント | マネジメント業務なし 完全土日休み フレックスタイム |
| リモートワーク | 不可 |
| 受動喫煙対策 | 喫煙室設置 |
| 更新日 | 2025/06/18 |
| 求人番号 | 4946813 |
採用企業情報
- SiTime Japan合同会社
-
- 会社規模非公開
- その他
-
会社概要
【本社所在地】東京都港区港南１丁目８−２７ 日新ビル ３階
【事業内容】微小電子機械システム（MEMS）及びアナログ半導体の研究及び開発
転職・求人情報の詳細をご覧になる場合は会員登録（無料）が必要です