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| 部署・役職名 | （設計技術統括部 － 旧設計・PDK技術部）Senior DFT Engineer |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
Job Description We are seeking a highly motivated and experienced Senior DFT Engineer to join our Enablement Team supporting the development of advanced semiconductor process technologies at the 2nm node and beyond. You will lead the Design－for－Test （DFT） implementation of large－scale test chips that are critical for enabling and validating our next－generation manufacturing processes. In this role, you will focus on scan insertion, ATPG, memory BIST, and other DFT methodologies, while also supporting yield analysis and EDA tool collaboration to improve design quality and test efficiency. You will work closely with RTL designers, physical design teams, process integration engineers, and EDA partners to ensure robust DFT infrastructure across our global sites. Responsibilities • Define and implement DFT architectures for technology development test chips, focusing on scan, boundary scan, and memory BIST. • Function and timing verification of implemented DFT circuit, evaluate test coverage with DFT simulation （ATPG, BIST, Fault simuation）. • Propose the best test solution with analysis among test coverage, test cost, test time • Collaborate with design teams to integrate DFT features from RTL through physical implementation. • • Develop and validate ATPG and MBIST patterns; support test bring－up and debug on silicon. • Analyze test data from silicon to identify systematic issues and improve process yield. • Engage with EDA vendors to evaluate and improve DFT tools and methodologies for advanced nodes. • Document best practices and contribute to the enablement of scalable DFT flows across future technology nodes. • Support cross－functional teams spanning design, process, product engineering, and reliability. |
| 応募資格 |
【必須（MUST）】 Minimum Qualifications• MS or PhD in Electrical Engineering, Computer Engineering, or a related field. • 5＋ years of experience in DFT development, preferably including advanced node designs or large－scale test chips. • Strong expertise in scan－based DFT, ATPG, compression, and memory BIST techniques. • Hands－on experience with commercial DFT tools （e.g., Synopsys TestMax, Siemens Tessent, Cadence Modus）. • Understanding of RTL－to－GDS flows and DFT timing considerations. • Practical experience in silicon bring－up, failure analysis, and yield improvement. • Excellent communication skills and the ability to work in a cross－site, cross－functional team. 【歓迎（WANT）】 Preferred Qualifications• Experience with DFT implementation for sub－5nm technologies. • Experience with DFT implementation for chiplet SOCs. • Familiarity with data analysis tools and methodologies used in yield learning. • Strong scripting ability （Python, Tcl, Perl） for automation of DFT and test flows. • Knowledge of test chip development for process technology enablement. • Japanese language proficiency is a plus but not required. |
| リモートワーク | 可 「可」と表示されている場合でも、「在宅に限る」「一定期間のみ」など、条件は求人によって異なります |
| 受動喫煙対策 | その他 「就業場所が屋外である」、「就業場所によって対策内容が異なる」、「対策内容は採用時までに通知する」 などの場合がその他となります。面接時に詳しい内容をご確認ください |
| 更新日 | 2025/06/17 |
| 求人番号 | 4942018 |
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