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| 部署・役職名 | （設計技術統括部 － 旧設計・PDK技術部）Test Chip Design Engineer （Physical Design ＆ PPA Analysis） |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
enabling the next generation of integrated circuits. We are seeking a highly skilled and experienced Test Chip Design Engineer to join our team. In this role, you will be responsible for the physical design and PPA （Power, Performance, Area） analysis of cutting－edge test chips, critical for validating and characterizing our advanced process technologies. You will play a pivotal role in bridging the gap between process development and product design, ensuring our technology offerings meet the demanding requirements of our global customers. This position offers a unique opportunity to work with the latest process nodes and design methodologies, contributing directly to the future of semiconductor manufacturing. Key Responsibilities As a Test Chip Design Engineer, your responsibilities will include: － Test Chip Physical Design and PPA Analysis: － Backend （BE） Implementation and Related Flow Development: Drive the full backend implementation flow, from chip－level planning and PG （Power/Ground） network design to floorplan, place, CTS （Clock Tree Synthesis）, route, power analysis （PDNA sign－off）, and comprehensive physical verification. － Design Methodology and EDA Tool Utility Development: Develop and enhance design methodologies and associated EDA tool utilities specifically for backend implementation. This includes creating solutions for challenges arising from new process technologies and developing utilities to support our customers effectively. － Technology Benchmark: Conduct detailed technology benchmarking to thoroughly understand and evaluate the PPA characteristics of new process technologies. － Collaborate closely with process development teams, circuit design teams, and EDA vendors to define and implement robust design flows. － Analyze and debug complex physical design issues, including timing, power, and physical verification failures. － Contribute to the continuous improvement of design processes and methodologies. － Document design specifications, methodologies, and results clearly and concisely. |
| 応募資格 |
【必須（MUST）】 Required Skills ＆ Experience :－ Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a related field. － 5＋ years of hands－on experience in digital backend IC design, with a strong focus on physical design and sign－off. － Proven expertise in the full physical design flow: floorplanning, power grid design, placement, clock tree synthesis （CTS）, routing, and physical verification （DRC/LVS/Antenna）. － Solid experience with power analysis （PDNA sign－off） and static timing analysis （STA）. － Proficiency with industry－standard EDA tools for physical design （e.g., Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, RedHawk, Calibre）. － Experience in scripting languages （e.g., Tcl, Python, Perl） for design automation and flow development. － Strong understanding of advanced CMOS process technologies and their impact on physical design. － Excellent analytical and problem－solving skills, with a keen eye for detail. － Business－level English proficiency, capable of technical discussions with international engineers. － English communication skills. 【歓迎（WANT）】 Preferred Skills ＆ Experience－ Experience in test chip design or IP development within a foundry environment. － Familiarity with advanced technology nodes （e.g., 7nm, 5nm, 3nm）. － Knowledge of FinFET or GAAFET architectures. － Experience with custom layout design or standard cell library development. － Prior experience in developing custom design methodologies or CAD utilities. － Understanding of reliability issues （e.g., EM, IR drop, ESD） from a physical design perspective. － Project leadership or mentoring experience. |
| リモートワーク | 可 「可」と表示されている場合でも、「在宅に限る」「一定期間のみ」など、条件は求人によって異なります |
| 受動喫煙対策 | その他 「就業場所が屋外である」、「就業場所によって対策内容が異なる」、「対策内容は採用時までに通知する」 などの場合がその他となります。面接時に詳しい内容をご確認ください |
| 更新日 | 2025/06/18 |
| 求人番号 | 4942011 |
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