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(設計技術統括部 - 旧設計・PDK技術部)Digital Chip Design Engineer (Standard Cell Development & DTCO)

年収:800万 ~ 1500万

ヘッドハンター案件

部署・役職名 (設計技術統括部 - 旧設計・PDK技術部)Digital Chip Design Engineer (Standard Cell Development & DTCO)
職種
業種
勤務地
仕事内容 We are looking for a talented and experienced Digital Chip Design Engineer to join our team, focusing on Standard Cell Development and Design Technology Co-Optimization (DTCO).

In this role, you will be instrumental in enabling high-performance and low-power digital chips for our next-generation products, by driving the convergence of library design and process technology. You will have the opportunity to work with state-of-the-art technology in a global environment, actively contributing to our advanced product development.

Key Responsibilities:
- Design, evaluate, and optimize standard cell libraries for advanced technology nodes.
- Plan and execute DTCO (Design Technology Co-Optimization) activities, strengthening the collaboration between circuit design and process technology to achieve optimal PPA (Power, Performance, Area) targets.
- Develop and improve custom layout, characterization, and verification flows.
- Design with a keen understanding of design rules, process variations, and reliability requirements.
- Collaborate closely with design teams, process and device development teams, and EDA teams.
- Evaluate and introduce new design methodologies and tools to meet PPA goals.
- Engage in technical discussions and collaborations with IP vendors and EDA venders.
- Document and maintain design data.
応募資格

【必須(MUST)】

Required Skills & Experience
- Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, Physics, or a related field.
- 5+ years of hands-on experience in digital IC design, specifically in custom cell, standard cell, or memory design.
- Proven design experience with advanced CMOS technology nodes (e.g., 7nm, 5nm, 3nm).
- In-depth knowledge and experience in standard cell library characterization and verification.
- Strong understanding of PDK (Process Design Kit) and design rules.
- Proficiency with EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, HSPICE, Spectre, PrimeTime, and Liberate
- Understanding of DTCO concepts and a strong willingness to contribute to related activities.
- Experience with scripting languages for automation (e.g., Python, Perl, Tcl).
- Excellent analytical and problem-solving skills.
- Business-level English proficiency, capable of technical discussions with international engineers.
- English communication skills.



【歓迎(WANT)】

Preferred Skills & Experience
- Practical experience or significant contributions to DTCO activities.
- Design experience with FinFET or GAAFET technologies.
- Knowledge of physical design (floor planning, place & route).
- Understanding of reliability issues (IR drop, EM, ESD, etc.).
- Experience applying machine learning or AI to design optimization.
- Team management or project leadership experience.

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更新日 2025/06/18
求人番号 4942004

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