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Place and Route (P&R) solutions' Applications Engineer

年収:1200万 ~ 1800万

ヘッドハンター案件

部署・役職名 Place and Route (P&R) solutions' Applications Engineer
職種
業種
勤務地
仕事内容 Seeking a dynamic, professional and technical individual, who will be responsible for technical selling and support of Mentor EDA’s leading-edge Place and Route (P&R) solutions.

The P&R Applications Engineer will be responsible for working with the account managers to determine the sales execution strategy by identifying and qualifying engagements based on customers’ needs and business opportunities, defining evaluations and/or benchmark criteria and executing the relevant technical campaigns to meet established goals, enabling Mentor P&R solutions’ adoption and deployment into customers’ production flows and providing best-in-class support to ensure customers’ success and broader use of Mentor P&R solutions.

※The job will Involve as much as 25% travel.

The responsibilities for the P&R AE role include, but is not limited to the following:

• Assisting Account Managers to determine sales execution strategy by identifying and qualifying the match-up between customer needs and Mentor EDA’s P&R solutions
• Creating and executing winning evaluations and benchmarking strategies and driving the relevant technical engagements to success and business win
• Supporting customers with deployment of P&R solutions and continued proliferation into broader design groups and user base
• Providing technical support to customers in both pre-sales and post-sales situations including technical problem resolution and training
• Communicating customers’ technical requirements to product marketing
労働条件 労働条件 ■雇用形態 正社員(試用期間:3ヶ月)

■予定年収 1200万円~1,800万円 (annual base salary: sales target incentive= 70:30)

■予定勤務地 東京都品川区

■勤務時間 9:00~18:00 (所定労働時間:8時間0分、休憩時間:60分)
■年間休日 120日、有給休暇10日~20日

■社会保険 健康保険、厚生年金保険、雇用保険、労災保険
応募資格

【必須(MUST)】

Job Qualifications
The successful candidate will possess the following combination of education and experience:
• Requires bachelor’s degree in EE, CE or VLSI
• 5+ years of industry experience in EDA or IC design space
• Expertise with Cadence Innovus, Synopsys IC Compiler I/II, Avatar Aprisa and/or Mentor Nitro-SoC
• Advanced FinFET process focused RTL to tape-out design flow knowledge
• Hands-on experience leading or working on IC design tape-out, P&R evaluations or benchmarking engagements
• Expertise in netlist to tape-out flow and meeting power-performance-area (PPA) and time-to-results (TTR) goals
• In-depth understanding of core P&R stages, root cause analysis and debugging (floorplanning, placement, clock tree synthesis, routing, signal and power integrity and static timing analysis)
• Must enjoy working with customers and cross-functional teams (sales, product management and R&D, marketing)
• Expert level TCL scripting and understanding of Verilog, UPF data formats
• Customer relationships and expectations management
• Technical campaigns and priorities management
• Strong communication skills
• Proactive self-starter with a focus on results
• Motivated team player/leader

更新日 2020/10/26
求人番号 1534016

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