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| 部署・役職名 | P＆R Applications Engineer |
|---|---|
| 職種 | |
| 業種 | |
| 勤務地 | |
| 仕事内容 |
The responsibilities for the P＆R AE role include, but is not limited to the following: ■Job Responsibilities 1. Assisting Account Managers to determine sales execution strategy by identifying and qualifying the match－up between customer needs and the EDA’s P＆R solutions 2. Creating and executing winning evaluations and benchmarking strategies and driving the relevant technical engagements to success and business win 3. Supporting customers with deployment of P＆R solutions and continued proliferation into broader design groups and user base 4. Providing technical support to customers in both pre－sales and post－sales situations including technical problem resolution and training 5. Communicating customers’ technical requirements to product marketing ■The P＆R Applications Engineer will be responsible for working with the account managers to determine the sales execution strategy by identifying and qualifying engagements based on customers’ needs and business opportunities, defining evaluations and/or benchmark criteria and executing the relevant technical campaigns to meet established goals, enabling the P＆R solutions’ adoption and deployment into customers’ production flows and providing best－in－class support to ensure customers’ success and broader use of the P＆R solutions. ■We are seeking a dynamic, professional and technical individual, who will be responsible for technical selling and support of the EDA’s leading－edge Place and Route （P＆R） solutions. |
| 労働条件 |
■雇用形態 正社員（試用期間：3ヶ月） ■予定年収 1,200万円～1,800万円 ■予定勤務地 東京都品川区 ■勤務時間 9:00～18:00 （所定労働時間：8時間0分、休憩時間：60分） ■年間休日 120日、有給休暇10日～20日 ■社会保険 健康保険、厚生年金保険、雇用保険、労災保険 |
| 応募資格 |
【必須（MUST）】 ■Job Qualificationsfollowing combination of education and experience: 1. Requires bachelor’s degree in EE, CE or VLSI 2. 5＋ years of industry experience in EDA or IC design space 3. Expertise with Cadence Innovus, Synopsys IC Compiler I/II, Avatar Aprisa and/or Mentor Nitro－SoC 4. Advanced FinFET process focused RTL to tape－out design flow knowledge 5. Hands－on experience leading or working on IC design tape－out, P＆R evaluations or benchmarking engagements 6. Expertise in netlist to tape－out flow and meeting power－performance－area （PPA） and time－to－results （TTR） goals 7. In－ depth understanding of core P＆R stages, root cause analysis and debugging （floorplanning, placement, clock tree synthesis, routing, signal and power integrity and static timing analysis） 8. Must enjoy working with customers and cross－functional teams （sales, product management and R＆D, marketing） 9. Expert level TCL scripting and understanding of Verilog, UPF data formats 10. Customer relationships and expectations management 11. Technical campaigns and priorities management 12. Strong communication skills 13. Proactive self－starter with a focus on results 14. Motivated team player/leader |
| 更新日 | 2020/10/19 |
| 求人番号 | 1525810 |
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- (2020/06/18)
