|部署・役職名||Memory Design Engineer and Manager|
Report To: Manager or Sr. Manager
＊Memory architecture design （SRAM, DRAM, MRAM, RRAM, PCRAM and eFlash）
＊Read and write critical path design and analysis
＊ Design of key building blocks （sensing, analog, high voltage, DFT）
＊Chip－level design verification
＊Embedded non－volatile memory compiler and productization
＊Co－work with product/reliability engineer on silicon characterization and reliability qualification
＊The candidates should have at least master degree with 3 years of experience or PhD degree in relevant field.
＊ Memory experts in the field of SRAM, non volatile memories, emerging memories （including RRAM, MRAM, PCRAM, FeRAM, etc）.
＊SRAM: the candidates should be familiar with bit cell characteristics （Vmin, bit cell performance, write margin）, sense amplifier design, high sigma variation analysis, race check, margin signoff. Knowledge on high speed and low Vmin design is a plus.
＊ Non volatile memorie: the candidates should be familiar with eFlash technology and design. The knowledge of analog design is a plus.
＊ Emerging memories: the candidates should be familiar the state of art of the development of new memories, with emphasis on both design and technology. The specific knowledge on MRAM, RRAM, PCRAM, FeRAM and analog circuit design is a plus.
＊Self－motivated in learning and problem－solving
＊ Good communication skill and a good team player
＊ Strong ownership and commitment