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Physical Design Manager & Engineer (ASIC/SoC Place & Route)

年収:800万 ~ 1200万

ヘッドハンター案件

部署・役職名 Physical Design Manager & Engineer (ASIC/SoC Place & Route)
職種
業種
勤務地
仕事内容 【Report To: Director or Sr. Manager
Responsibilities:
*Perform the following:
- Chip/Block level floorplan,
- Clock tree synthesis,
- Place & Route,
- RC extraction,
- STA, timing closure,
- IR/EM analysis and fix,
- DRC/LVS/ERC analysis and fix,
- Tape-out sign off.
- Customer on-site support.
応募資格

【必須(MUST)】

Requirements:
*Education:
- Bachelor/Master’s degree in Electrical Engineering or Computer Science.
*5-15 years Netlist (or RTL)-GDS physical implementation experience.
*Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
*In depth knowledge of major EDA tools/design flows.
*Experience with TSMC N16 or below technology.
*Experience in block level implementation, chip integration and signoff.
*Experience in Perl/TCL language programming.
*Proven record in multi-million gate design production tapeouts.


【歓迎(WANT)】

*Experience in any of the following is a plus:
- FinFet Design
- TSMC N7 and below technology.
- Low-power implementation methodology.
- Advanced timing signoff methodology.
- Independently complete Netlist-GDS P&R, signoff task.


*Personal Attributes:
- Aggressive in learning and problem-solving.
- Good communication skill and a good team player.
- Strong project ownership and commitment.
- Self-motivated and can work independently.
更新日 2019/10/31
求人番号 1158668

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